Product Summary

The EDJ1116DJBG-DJ-F is a 1G bits DDR3 SDRAM.

Parametrics

EDJ1116DJBG-DJ-F absolute maximum ratings: (1)Power supply voltage, VDD: -0.4 to +1.975 V; (2)Power supply voltage for output, VDDQ: -0.4 to +1.975 V; (3)Input voltage, VIN: -0.4 to +1.975 V; (4)Output voltage, VOUT: -0.4 to +1.975 V; (5)Reference voltage, VREFCA: -0.4 to 0.6 × VDD V; (6)Reference voltage for DQ, VREFDQ: -0.4 to 0.6 × VDDQ V; (7)Storage temperature, Tstg: -55 to +100℃; (8)Power dissipation, PD: 1.0 W; (9)Short circuit output current, IOUT: 50 mA.

Features

EDJ1116DJBG-DJ-F features: (1)Double-data-rate architecture; two data transfers per clock cycle; (2)The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture; (3)Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver; (4)DQS is edge-aligned with data for READs; centeraligned with data for WRITEs; (5)Differential clock inputs (CK and /CK); (6)DLL aligns DQ and DQS transitions with CK transitions; (7)Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS; (8)Data mask (DM) for write data; (9)Posted /CAS by programmable additive latency for better command and data bus efficiency; (10)On-Die Termination (ODT) for better signal quality, Synchronous ODT; Dynamic ODT; Asynchronous ODT; (11)Multi Purpose Register (MPR) for temperature read out; (12)ZQ calibration for DQ drive and ODT; (13)Programmable Partial Array Self-Refresh (PASR); (14)/RESET pin for Power-up sequence and reset function; (15)SRT range: Normal/extended; Auto/manual self-refresh; (16)Programmable Output driver impedance control.

Diagrams

EDJ1116DJBG-DJ-F block diagram

EDJ1104BASE
EDJ1104BASE

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Data Sheet

Negotiable 
EDJ1104BBSE
EDJ1104BBSE

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Data Sheet

Negotiable 
EDJ1108BABG
EDJ1108BABG

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Data Sheet

Negotiable 
EDJ1108BASE
EDJ1108BASE

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Data Sheet

Negotiable 
EDJ1108BBSE
EDJ1108BBSE

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Data Sheet

Negotiable 
EDJ1116BABG
EDJ1116BABG

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Data Sheet

Negotiable